Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to an extensible configurable FPGA storage structure and an FPGA device.
Related Art
A Field-Programmable Gate Array (FPGA) is a logic device that has abundant hardware resources, a powerful parallel processing capability and a flexible reconfigurable capability. With these features, the FPGA is increasingly widely used in many fields such as data processing, communications and networks.
A local memory is an extremely important on-chip resource type of the FPGA. Design of a local memory architecture is directly related to scalability and flexibility of logic performance and storage performance of the FPGA. In an FPGA architecture, there are mainly two types of structures that provide a data storage function: registers and block memories. The registers are dispersed in the FPGA, and together with lookup tables (LUTs), constitute basic units of the FPGA architecture, i.e., programmable logic blocks (PLBs). Each register has its own clock, enable, reset and data input/output ports. The block memories, as FPGA-centralized data storage units, have a relatively large capacity (usually a dozen Kb to dozens of Kb), and the capacity of the block memory is fixed, so that large-scale storage structure design can be achieved.
Based on the existing local memory architecture, when it is necessary to achieve small-capacity (e.g., a few Kb) memory design, if the design is implemented by using registers, it is necessary to additionally consume a large number of lookup tables to achieve address write/read control logic; and if the design is implemented by using block memories, additional consumption is unnecessary, but it will cause a waste of storage resources.